1. Field
Example embodiments relate to a semiconductor package, for example, to a chip stack, a chip stack package, and method of forming a chip stack and chip stack package.
2. Description of the Related Art
Semiconductor memory devices, for example, dynamic random access memory (DRAM), have been developed to increase operating speeds and capacity (product capacity). In order to achieve higher capacity, a method of stacking the chips may be used. The capacity of a semiconductor memory device using a stacked chip structure may be increased in proportion to the number of chips in the same package area.
FIG. 1 is a sectional view illustrating a conventional chip stack package.
In particular, a conventional chip stack package may be formed by stacking two chips 12 and 22 on an upper surface 32 of a wiring (interconnection) substrate 30. An adhesive layer 38 may be interposed between the chips 12 and 22. Chip pads 14 and 24 formed on the chips 12 and 22, respectively, may be electrically connected to a wiring pad 16 of the wiring substrate 30 by bonding wires 36. The chips 12 and 22 may be mounted on the upper surface 32 of the wiring substrate 30. A molding compound 40 may be formed on the resulting chip stack structure which may protect the bonding wires 36. External connection terminals 42 may be formed on a lower surface 34 of the wiring substrate 30. The external connection terminals 42 may be electrically connected to the chip pads 14 and 24 by an internal wiring (interconnection) 28.
In a conventional chip stack package, an input capacitive load of an external connection terminal 42 may be increased as compared to an input capacitive load in a single chip package, e.g., a package having one embedded chip. By way of example, in a conventional chip stack package, because two chip pads 14 and 24 in parallel may be connected to one external connection terminal 42, an input capacitive load may be doubled as compared to that of a single chip package. The input capacitive load may increase in proportion to the number of stacked chips.
However, if the input capacitive load of a conventional chip stack package is increased, the operating speed of the conventional chip stack package may be decreased. For example, in the operation of a conventional chip stack package, one chip may be operating while the other chip may be turned off to reduce heat. The chip pads 14 and 24 may both be connected to one external connection terminal 42. Thus, the input capacitive load may be increased, thereby decreasing the operating speed of the conventional chip stack package.